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- Article name
- CONFIGURABLE HARVARD ARCHITECTURE OF MULTICORE PLATFORM DSP-CORES
- Authors
- Belyaev А. А., , bel@elvees.com, Elvees R&D Center, Moscow, Russia
- Keywords
- digital signal processing / system on a chip (SOC) / DSP-cores / Harvard architecture / program memory / data memory / configurability
- Year
- 2011 Issue 2 Pages 7 - 10
- Code EDN
- Code DOI
- Abstract
- Configurable Harvard architecture of ELcore-xxTM family DSP-cores of MULTICORE platform is considered. Configurable organization of program and data memory of these DSP-cores permits to fit it to custom application requirements.
- Text
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